Research Paper
Year: 2020 | Month: September | Volume: 7 | Issue: 9 | Pages: 367-373
Design and Implementation of Optimized Reversible 4-Bit Linear Feedback Shift Registers for Computing Applications
Chandrasekhar Rao Jetti1, Hari Chandana Earla2, Harish Kumar Goli3
1Associate Professor, Bapatla Engineering College, Bapatla, A.P., India
2,3Scholars, Bapatla Engineering College, Bapatla, A.P., India
Corresponding Author: Chandrasekhar Rao Jetti
ABSTRACT
Reversible logic has emerged as a major area of research in recent years due to its ability to reduce power dissipation which is the main requirement in the low-power VLSI. Reversible Computing has shown greater impact to have enormous applications in emerging technologies such as Quantum Computing, QCA, Nanotechnology and Low Power VLSI. In this paper, we have realized Optimized Reversible Linear Feedback Shift Registers (LFSR) and have explored it in terms of delay, quantum cost, garbage outputs. We have shown a new reversible realization of Serial Input Serial Output (SISO) and Serial Input Parallel Output (SIPO) registers up to N-bit for the design of LFSR. Proposed circuits have been simulated using Vivado 2016.4 and synthesized by using FPGA Nexys-4 DDR.
Keywords: Reversible Logic, SISO-Serial Input Serial Output, SIPO-Serial Input Parallel Output, Quantum Computing, Reversible LFSR-Linear Feedback Shift Register.
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