Research Paper
Year: 2022 | Month: November | Volume: 9 | Issue: 11 | Pages: 40-45
DOI: https://doi.org/10.52403/ijrr.20221106
Low Power Full Scan Architecture for UART Module
Abhinav S1, Kiran V2
1Student, Department of Electronics and Communication Engineering, R V College of Engineering, Mysore Road, RV Vidyaniketan, Post, Bengaluru, Karnataka, India-560059
2Associate Professor, Department of Electronics and Communication Engineering, R V College of Engineering, Mysore Road, RV Vidyaniketan, Post, Bengaluru, India-560059
Corresponding Author: Abhinav S
ABSTRACT
Modern SoCs feature a complicated design made up of many macros that are in charge of various tasks carried out by an application. The effort required for the verification and testing of a specific product grows as a result of the requirement for more raw computing power and an increase in integration density. The testability of the communication modules is required because SoCs contain several communication modules that, if they fail, could render the SoC worthless. The full scan architecture for a full-duplex UART module is the one that is being suggested. The work displays the power savings for both manually and automatically inserted scan chains that were based on the system partition algorithms. While manually placed scan chains achieved peak power reduction of 74.9 percent in comparison to automatic scan chains, the automatically inserted scan chains have less area with higher activity.
Keywords: Low power, full scan, UART, DFT, System partition algorithms
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